1. Field of the Invention
The invention relates to integrated circuit devices, and more particularly to static random access memory (SRAM) integrated circuits providing user selectable operating speed, noise immunity, or power consumption.
2. Description of the Prior Art
SRAMs hold advantages in speed and power demand over comparable capacity dynamic random access memories (DRAMs). Memory cells in SRAMs are based on latches instead of capacitors as in DRAMs. Capacitors dissipate a charge (corresponding to a bit of data) over time and thus require periodic refresh. Refresh requires power. Reading and writing to a capacitor based memory device requires both time and power. Thus, SRAMs have been advantageously used in applications requiring high speed operation (e.g. cache memory for personal computers), or low power consumption (e.g. portable computers powered by batteries). In addition, SRAM integrated circuits are simpler to use than competing DRAMs because DRAMs require complex circuitry for clocks and refresh operations. Thus SRAMs have been favored where the improved performance justifies their greater expense, or in basic electronic components where the incremental design cost to handle refresh is unjustified.
To further enhance SRAM operating speed, edge transition detection circuits have been integrated with the address decoding circuitry of SRAM devices. Edge transition detection provides a pulse to internally synchronized components of an SRAM in response to leading edge transitions in the state of any of a set of address or control signals. This can be used for controlling precharging and equilibration operations within the SRAM preparatory to reading or writing of data. However, while useful for high speed operation, edge transition detection tends to increase on chip noise and power consumption. In some applications, users may wish to trade speed for less noise and lower power consumption. However, rather than providing two distinct SRAM designs, it would be convenient to be able to reprogram or reconfigure one SRAM type to elect or not elect edge transition detection operation.